BX -- AArch32

BX

Branch and Exchange causes a branch to an address and instruction set specified by a register.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

m = UInt(Rm);

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	0	0	0	1	1	1	0	Rm				(0)	(0)	(0)

m = UInt(Rm); if InITBlock() && !LastInITBlock() then UNPREDICTABLE;

For more information about the constrained unpredictable behavior, see Architectural Constraints on UNPREDICTABLE behaviors.

<c>	See Standard assembler syntax fields.

<q>	See Standard assembler syntax fields.

<Rm>	For encoding A1: is the general-purpose register holding the address to be branched to, encoded in the "Rm" field. The PC can be used.
	For encoding T1: is the general-purpose register holding the address to be branched to, encoded in the "Rm" field. The PC can be used. Note If <Rm> is the PC at a non word-aligned address, it results in unpredictable behavior because the address passed to the BXWritePC() pseudocode function has bits<1:0> = '10'.

if ConditionPassed() then EncodingSpecificOperations(); BXWritePC(R[m], BranchType_INDIR);

Internal version only: isa v01_31, pseudocode v2023-06_rel, sve v2023-06_rel ; Build timestamp: 2023-07-04T18:06